Electronic doorbell circuit based on an ATtiny85
In this article I will explain the operation of an electronic doorbell circuit based on the ATtiny85. The doorbell circuit can produce a realistic-sounding bell effect by generating a sine wave with a decaying amplitude. When the circuit is activated, the device first produces a 720Hz bell sound, followed by a 580Hz bell sound. When the doorbell is not ringing, the ATtiny goes into sleep mode to reduce the power consumption.
Since the ATtiny does not have an analog output, I will also describe how the ATtiny can be made to output an analog voltage.
The source code, schematic files, and PCB files for this project can be found at https://github.com/mnigmann/doorbell
Decaying sine generation
The decaying sine waveform is generated by storing a 16-bit fixed-point complex number and repeatedly multiplying that complex number by a constant value. Due to a property of complex multiplication, this results in the complex number rotating around the origin of the complex plane, and decreasing in magnitude with every step. The real part of this complex number will be a decaying sine. The details of this algorithm can be found here. In summary, producing a decaying sine wave requires one complex multiplication per sample.
Schematic
Generating an analog signal
In order to produce a realistic-sounding bell, the doorbell circuit must be able to generate a sine wave. Since the ATtiny85 has no digital-to-analog converter, the circuit must somehow convert the pulse-width modulated (PWM) output of the ATtiny85 to an analog voltage. This is done by passing the PWM output of the ATtiny85 through an integrator circuit (R2, C2, left half of U1) and low-pass filter (R5 and C5) and feeding the output of the integrator back into the ATtiny85, creating a feedback loop. As a result, the rate of change of the output waveform is determined by the setting of the PWM output. Finally, the output of the low-pass filter is amplified by Q1 and Q2 and fed into the speaker.
The frequency of the PWM output is 100kHz, and the duty cycle is 100% when the PWM output is set to 159, and the duty cycle is minimum (0.625%) when the output is set to 0. The PWM setting is updated 8000 times per second, giving a sample rate of 8kHz.
The non-inverting input of the left half of U1 is connected to a voltage divider (R1 and R3) which puts it at about half of the supply voltage. Thus, one would expect that when the PWM output is set to 79, the output of the integrator does not change. However, due to variations in the resistances of R1 and R3, the actual center may be different. In this article, this center point is 76. Furthermore, the parameter \(\alpha\) relates the difference between the PWM setting and the PWM center point to the expected change in the measured voltage. For example, if \(\alpha=4\) and \(PWM=80\), then we would expect the difference between successive ADC measurements to be 16. We would also expect the voltage to be decreasing as the integrator is an inverting integrator.
Normal operation
Consider what happens at the open circle in the green box. At that time, only the previous measurement will be available, as the ADC is not fast enough for real-time measurement. Thus, the program estimates the current voltage from the previous voltage and the previous PWM setting. For this, we use the formula \(V_t = V_{t-1} + \alpha\left(76-PWM_{t-1}\right)\), where \(V_{t-1}\) is the previous ADC measurement and \(PWM_{t-1}\) is the previous PWM setting. To account for what happens when the output of the integrator reaches the supply voltage, \(V_t\) is limited to numbers between 0 and 1023.
Next, the next PWM value is calculated from the difference between the estimated voltage and the target voltage. This is done with the formula \(PWM_t=76+\alpha^{-1}\left(V_t-V_T\right)\), where \(V_T\) is the target voltage.
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