Third version of the PWM dimmer and test results

In this article I will present the third version of the PWM dimmer I have described in previous articles. I have made major changes to the control circuit, the topology of the dimmer, and the construction of the device. I will also quantitatively compare the performance of the dimmer to previous versions and to a phase control dimmer.

Schematic

Topology

The previous versions of the dimmer used only one transistor and one rectifier, switching the live connection through a filter network. This method worked, but was very inefficient and caused the MOSFET and the inductors to dissipate alot of power. This version uses two MOSFETS, one switching the output to live and the other switching it to neutral. The schematic is shown below:
The circuit now consists of two MOSFETS in a half-bridge. The gate drive circuit and the MOSFET/rectifier circuit have not changed since the last revision.

Filter

The 600uH inductor and 100nF capacitor form a filter similar to one found in a buck converter. When the upper MOSFET is on, energy is stored in the 600uH switching inductor, and when the lower MOSFET is on, the inductor discharges into the 100nF capacitor. The inductor is made of the primary from a flyback transformer from a power supply. The 2.2nF capacitor acts as a snubber that provides a path for the current in the inductor during the dead time (the interval between one transistor switching off and the other switching on).

The input inductor has been replaced with a significantly larger 1mH inductor, which decreases the amount of electromagnetic noise generated by the dimmer.

Control circuit

The dimmer uses one PH9572-111 gate drive transformer for each MOSFET. The circuit between the transformer and the MOSFET has not changed.

The control circuit has changed significantly as it must now drive two gates with a dead time between them. The schematic is shown below:

gEDA schematic file | Link to simulation

The NOR gates, the 21.5k resistor, the potentiometer, and the 3.9nF capacitor form the variable duty cycle oscillator and dead time generator circuit. All of the NOR gates are wired as inverters. Let A, B, C, and D be the outputs of the bottom-right, bottom-left, top-left, and top-right NOR gates respectively. All of the The oscillator works as follows:

  1. Suppose A and C are high and B and D are low. Also suppose the capacitor is discharged.
  2. The capacitor will begin to charge through the top diode and the bottom half of the potentiometer until the voltage on the right side of the capacitor reaches the threshold voltage of the bottom-right NOR gate.
  3. A goes low and B goes high. However, the 21.5k resistor and the input capacitance of the top-left NOR gate causes a delay, so the top NOR gates switch only slightly after the bottom ones. This delay is equal to the dead time.
  4. The capacitor discharges through the bottom diode and the top half of the potentiometer until the voltage on the right side of the capacitor reaches the threshold voltage of the bottom-right NOR gate.
  5. The bottom gates switch, followed shortly by the upper gates.
  6. The cycle repeats.
Due to the behavior described above, C is equal to A but with a small delay, and D is equal to B with a small delay. The dead time generator works by turning off both MOSFETs when A is not equal to C or when B is not equal to D. The waveforms of A, B, C, and D can be seen below:

GDT2 is high when A and C are high, or equivalently, when A is high and D is low. This comparison can be implemented with a single NPN transistor (Q5) with its base connected to A and its emitter connected through a resistor to D. When A is higher than D, Q5 acts as a current source that draws current from the base of Q4, turning it on. R4, C5, and D6 help Q4 turn off faster. Note that A goes low before D goes high, and Q4 must turn off whenever either happens. C5 couples the rising edge of B (the complement of A) to the base of Q4, which turns it off more quickly than just removing the current from its base.

GDT2 should be low whenever either A is low or C is low. However, the lower transistor Q6 is only on while D is high (or C is low), and remains off while C is high and A is low. Instead, the circuit relies on the current stored in the gate drive transformer to switch. When Q4 turns off, the current will continue to flow through a diode across Q6 (TODO). C7 helps Q6 turn off by coupling the negative edge of D directly to the transistor.

Physical construction of the device

The dimmer consists of two parts: the high voltage section, containing the MOSFETs, switching inductor, and gate drive transformers, and the control section. The high voltage section is enclosed in a junction box, with both MOSFETs mounted to the junction box for heatsinking. The junction box also helps to contain electromagnetic noise generated by the dimmer. The dimmer is spliced into the middle of an extension cord (technically a IEC cable with a plug socket attached to it).

Data collection

The methodology for assessing the performance of the dimmer is the same as for the previous version.

Noise level

The following plot has the rotational speed (in tens of RPM) on the x-axis and the measured sound level (in dB) on the y-axis. For example, an x-value of 100 would correspond to 1000 RPM.

Efficiency of the dimmers

The following plot has the rotational speed (in tens of RPM) on the x-axis and the real power drawn by the dimmer and fan on the y-axis. The real power was calculated by multiplying the 60Hz component of the current waveform by 120V. This plot would indicate that the PWM dimmer v3 is significantly more efficient than the phase control dimmer, but I think this may be due to measurement error. I also reused the data collected for the other dimmers from previous tests. My power factor measurements also only measured the distortion power factor, so I may have over-estimated the real power consumption of the phase control dimmer.

Power factor with fan

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