Divide-by-n counter with a fixed duty cycle

A divide-by-n counter is a circuit that takes a digital clock signal with a frequency f and a number n and produces a digital output signal with a frequency of f/n. For example, the waveforms below are the input and output of a divide-by-5 counter that produces an output pulse every 5 input pulses.

However, this approach produces a output waveform with a duty cycle that decreases as n increases. In some cases, it may be necessary to produce an output with an exact 50% duty cycle that does not change with n:

In this article, I will describe a 9 bit divide-by-n counter circuit (where n is between 2 and 511) that produces an output with a 50% duty cycle.

Note on reference designators: Many logic chips contain multiple copies of the same circuit (for example, 74HC00 NAND chip). Each copy will be shown individually, but will have the same reference designator. To distinguish these copies, the lowest pin number belonging to that copy will be placed in brackets after the reference designator. For example, the gates a 74HC00 with reference designator U1 will be referred to as U1[1], U1[4], U1[8], and U1[11]

Schematic and operation

The schematic is shown below:
Link to simulation | gEDA schematic file

Operation of the 40103 chip

The 40103 chip used in this circuit is a presettable down counter. The chip contains an internal counter, and whenever the internal counter is equal to 0, the CO output is low. The value on the J0-J7 inputs can be loaded asynchronously (immediately) to the internal counter by driving the APE input low. Alternatively, the internal counter can be loaded synchronously if the SPE input is low while a rising edge occurs on the clock input.

When n is even

When n is an even number, then the general approach is to toggle the output every n/2 input clock cycles. When n is even, D0 is 0, so the output of U2[1] is high. The CO output is connected via U2[8] (which acts as an inverter) and U2[4] (which also acts as an inverter because pin 4 is high) to the APE input. As a result, as soon as the internal count reaches zero, the internal counter is automatically and immediately preset to n/2 (which can be easily computed by simply ignoring the least significant bit and shifting the rest down). The CO output is connected to the clock input of a D-type flip-flop which is configured to change state every clock pulse. For example, with n=4 (i.e. D0=0, D1=0, D2=1), one gets the following waveforms:

The internal counter is only zero for a very short period of time, because as soon as the CO output goes low, the counter is preset and is thus no longer zero. The pulse on CO is too short to be properly represented on the diagram, and the internal counter is never shown to be zero.

When n is odd

When n is odd, the general approach is to switch the output on for (n-1)/2 cycles and switch it off for (n+1)/2 cycles and then correct the duty cycle of the output by switching the output on half a cycle early. When n is odd, D0 is 1, so only when the Q output of U1[1] is low is the output of U2[1] high. In this case, the circuit behaves as it would when n is even, and the counter is preset to (n-1)/2 as soon as the internal counter becomes zero. Thus, the Q output of U1[1] is low for exactly (n-1)/2. However, when the Q output is high, the output of U2[1] is low and the output of U2[4] is forced high. As a result, the counter cannot be immediately preset when the counter is zero. However, when CO goes low, so does the SPE input, and the counter is preset after being zero for exactly one cycle. Thus, the Q output of U1[1] is high for exactly (n+1)/2 cycles.

However, the duty cycle of the output is not 50%. To correct for this, the output is turned on half a cycle early. When CO is high, the preset input of U1[8] is kept low, so its output is high. Thus, whenever the Q output of U1[1] is high, its Q output is low, so the output of U2[11] is also high. However, if the CLR input to U1[8] goes low while its PRE input is high, its Q output turns off, and the output of U2[11] is forced high. Since the PRE input is connected to CO via an inverter, this will occur at the at the end of the off-time:

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