Divide-by-n counter with a fixed duty cycle
A divide-by-n counter is a circuit that takes a digital clock signal with a frequency f and a number n and produces a digital output signal with a frequency of f/n . For example, the waveforms below are the input and output of a divide-by-5 counter that produces an output pulse every 5 input pulses. However, this approach produces a output waveform with a duty cycle that decreases as n increases. In some cases, it may be necessary to produce an output with an exact 50% duty cycle that does not change with n : In this article, I will describe a 9 bit divide-by-n counter circuit (where n is between 2 and 511) that produces an output with a 50% duty cycle. Note on reference designators: Many logic chips contain multiple copies of the same circuit (for example, 74HC00 NAND chip). Each copy will be shown individually, but will have the same reference designator. To distinguish these copies, the lowest pin number belonging to that copy will be placed in brackets after the refere