People counter made from discrete components

In a previous article, I described how I created a people counter that used capacitive sensing. In this article, I will describe the operation of a people counter I made from discrete components that works on a similar principle. As described in the previous article, this circuit will contain two separate oscillators, with each one connected to a sense wire. However, in this circuit, one of the oscillators will be a voltage controlled oscillator (VCO). A frequency comparator will compare the frequencies of the two oscillators and tune the VCO so they match.

Schematic and explanation

Regulator

U1 regulates the 12 volt input into the 5 volts needed for the logic gates. The capacitors C1 and C2 are actually placed near the power pins of U2 and U3.

Reference oscillator (bottom left box)

The reference oscillator oscillates independently of any other signal, except for the capacitance on the sense wire. The circuit is identical to the one described in the previous article, except for R9. R9 was added to decrease the amplitude of the oscillation in the resonant circuit. The intention was to cut down on any "ringing" on the collector of Q3 that would be interpreted by the frequency comparator as another transition/cycle. In the image below, the ringing is visible near the falling edge:

VCO (top left box)

It was noted that when a magnet was held near the inductor of the reference oscillator, the frequency of the oscillator increased. Thus, to build the VCO, I wrapped a coil around the inductor to create an electromagnet. One would think that as the current through the electromagnet increased, the frequency would increase (according to my simulations, this is what should happen). However, in reality, the frequency decreased, and I am not sure why. I suspect that the actual effect was that the current source clamped the oscillations in the resonant circuit, which changed the frequency.
In the schematic, this electromagnet is represented by T1. Q2 and R5 form a constant current source whose magnitude is controlled by the transistor's base voltage. This is determined by the setting of the potentiometer R4 and the feedback from R10. C5 smooths the feedback signal so the current through the transformer is DC.

Frequency comparator (right box)

Let \(f_r\) be the frequency of the reference oscillator and \(f_v\) be the frequency of the VCO.

Case 1: \(f_v \lt f_r\)

It would take \(\frac{n}{f_r}\) seconds for \(n\) cycles of the reference oscillator to occur. Similarly, \(n\) cycles of the VCO would occur in \(\frac{n}{f_v}\) seconds. If \(f_v \lt f_r\), then \(\frac{n}{f_v} \gt \frac{n}{f_r}\). Thus, the rising edge of the reference oscillator will always occur before the corresponding rising edge of the VCO. The time delay between these increases with time, which gives the appearance of the VCO waveform shifting to the right with respect to the reference waveform. This is visible in the image below, where the green waveform is the reference oscillator and the red waveform is the VCO:
Note that towards the right side of the image, the red waveform touches the rising edge of the green waveform. In the schematic, reference oscillator is connected to the clock of U2[1], whereas the VCO is connected to the data pin. As a result, the output of U2[1] (green waveform below) goes high:
Since the waveform of the VCO appraches the waveform of the reference oscillator from the left, when the output of U2[1] goes high, they will be out of phase. As a result, the duty cycle of the logical AND (red waveform in the image above) of these two signals will be low

Case 2: \(f_v \gt f_r\)

On the other hand, when \(f_v \gt f_r\), the waveform of the VCO will appear to shift to the left with respect to the waveform of the reference oscillator, as is visible in the image below
Note that near the right side of the image, the red waveform begins to touch the rising edge of the green waveform. However, since the red waveform is approaching from the right, the two signals will be in phase when they touch. Therefore, on the rising edge of the output of U2[1] (green below), the duty cycle of the logical AND of the two signals (red below) will be high.


The output of the AND gate is connected to a filter network, which converts the varying duty cycle into a varying voltage. On the rising edge of the output of U2[1], the duty cycle will be higher or lower, depending on whether the VCO is faster or slower than the reference oscillator. U2[8] stores this information, and thus, if \(f_v \gt f_r\), the output of U2[8] (COMP) is high, and if \(f_v \lt f_r\), the COMP is low.

Theory

When the circuit starts up, the reference oscillator starts oscillating at a frequency of \(f_r\). Since C5 starts discharged, the frequency of the VCO \(f_v\) starts higher than \(f_r\), so COMP is high. As C5 charges, the \(f_v\) decreases, until it goes below \(f_r\). Then, COMP goes low, and the frequency increases again. Once \(f_v\) goes above \(f_r\), COMP goes high, and the cycle repeats. As a result, COMP becomes a PWM signal whose duty cycle is proportional to the \(f_r\). When the circuit is in this state, \(f_r \approx f_v\). Assuming \(f_r\) does not change by too much, the circuit is always in this state. Additionally, since the resistance of R10 is much greater than R4, the duty cycle of COMP has to change by much more to compensate, creating some gain.

Suppose a person approaches the sense wire connected to the reference oscillator. This causes the frequency of the reference oscillator to decrease. The duty cycle of COMP increases to drive the \(f_v\) down to match \(f_r\).

Suppose a person approaches the sense wire connected to the VCO. The frequency of the VCO decreases, so the duty cycle of COMP decreases. This causes the frequency of \(f_v\) to increase again to match \(f_r\)

R2 and C3 filter this duty cycle, turning it into a DC voltage. From the above statements, when the voltage on C3 increases, then decreases, a person walked past the device in one direction. When the voltage on C3 decreases, the increases, a person walked past the device in the other direction. An additional circuit that is not shown in the schematic would be needed to decode these patterns.

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